In the packaging of integrated circuits, dies may be packaged onto package substrates, which include metal connections that are used to route electrical signals between opposite sides of the package substrates. The dies may be bonded onto one side of a package substrate using flip chip bonding, and a reflow is performed to melt the solder balls that interconnect the dies and the laminate substrate.
The package substrates may use materials that can be easily laminated. In addition, organic materials may be used as the dielectric materials of the package substrate. These materials, however, are prone to the warpage caused by the elevated temperatures used in the reflow of the solder. Furthermore, during the bonding process, since the dies and the package substrates have significantly different coefficients of thermal expansion (CTEs), the warpage in the dies and the package substrates is worsened. For example, the silicon in the dies may have a CTE of 3.2, while the package substrates may have a CTE between about 17 and 20, or even higher. The warpage in the package substrates may cause irregular joints and/or bump cracks. As a result, the yield of the packaging process is adversely affected.